A so-called three-dimensional integrated circuit has the following structure. That is, a plurality of semiconductor chips are layered on each other, and a TSV (Through-Silicon Via), a microbump, or the like is used to connect the semiconductor chips.
The three-dimensional integrated circuit is formed by vertically layering a plurality of semiconductor chips on each other, and thus has a shorter wiring length than an integrated circuit formed by horizontally layering a plurality of semiconductor chips on each other. The power consumption of a circuit, which is proportional to an operating frequency, is reduced as the total wiring length of the circuit is shortened. For this reason, the three-dimensional integrated circuit is particularly useful in a processor having a high operating frequency.
In the three-dimensional integrated circuit, if the load on a semiconductor chip changes, the supply voltage of another semiconductor chip may drop. The drop in supply voltage is more likely to occur in a high-performance processor that consumes a large amount of current.
Accordingly, a capacitor is provided on a substrate on which the three-dimensional integrated circuit is mounted, so that the electric charge accumulated in the capacitor can compensate the voltage drop, and the voltage on the load is stabilized. Such a capacitor is referred to as “decoupling capacitor”.
However, when the capacitor is provided on the substrate, the wiring from the capacitor to the load becomes long. As a result, the value of inductance becomes large. When the inductance is large, the amount of charge that flows into the load is decreased. In this case, the capacitor does not effectively serve as a decoupling capacitor.
Patent Literature 1 discloses a technique for arranging a decoupling capacitor in the vicinity of a load. A semiconductor device according to Patent Literature 1 is a layered semiconductor device including a plurality of chips that are layered on each other. Also, a film-like capacitor is provided between the chips so as to form a decoupling capacitor in the vicinity of each chip.